Flash initiative wear leveling algorithm

A non-volatile memory device comprising:

• a memory array, the memory array including a plurality of memory blocks, each memory block having a physical block address. and each memory block either having a logical block address or being a spare block;
• a memory controller coupled with the memory array, the memory controller to control the storage of data in the memory array;
• and
• one or ore registers to record the number of erase operations for the plurality of memory blocks of the memory array, the one or more registers including a count of erase cycles for each physical block address and a count of erase cycles for each logical block address.

A computer system comprising:

• a bus;
• a flash memory device coupled with the bus, the non-volatile memory device including a plurality of memory blocks;
• a dynamic random access memory coupled with the bus;
• and
• a processor coupled with the bus, the processor to transfer data between the dynamic random access memory and the flash memory device;
• wherein the system tracks the number of erase cycles for each of the memory blocks by physical block address and by logical block address.

A computer-readable medium having stored thereon data representing sequences of instructions that, when executed by a processor. cause the processor to perform operations comprising:

• counting erase cycles for each of a plurality of memory blocks of a flash memory, the counting of erase cycles for a memory block including:
• incrementing a first count for a physical block address of the memory block, and
• if the memory block is not a spare memory block. incrementing a second count for a logical block address of the memory block;
• and
• determining whether the flash memory has uneven wear of memory blocks based at least in part on the counting of the erase cycles of the plurality of memory blocks.