Multiple slot memory system

A memory system comprising:

• a memory controller;
• one or more registered memory modules coupled to the memory controller, each registered memory module having a bank of memory chips and an associated register;
• a pre-register address/command bus connecting the memory controller with the associated register of the one or more registered memory modules;
• and
• a post-register command/address bus connecting in parallel the bank of memory chips with the associated register of the one or more registered memory modules, the post-register command/address bus terminating with termination resistors that are coupled to a voltage level that is approximately half of the supply voltage level of the one or more registered memory modules;
• wherein the memory controller provides chip select signals to the associated register of the one or more registered memory modules, and the associated register of the one or more registered memory modules switches command/address signals to the bank of memory chips independent of a state of the chip select signals.