US 2010/0161866 A1Published application

Logic controller having hard-coded control logic and programmable override control store entries

AssigneeUnisys Corporation

InventorsRoss M. Weber, David R. Spatafore

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Abstract

Control logic of a node controller receives an input vector and produces an output vector. The control logic includes a plurality of tied control store entries including hard-coded logic to identify unique values of the input vector and to produce the output vector from a hard-coded output vector when the input vector is identified and when the tied control store is enabled. The control logic also includes a plurality of spare control store entries including programmable logic configurable to identify values of the input vector and to produce the output vector from a programmable output vector when the input vector is identified and when the spare control store is enabled. One of the spare control store entries that is configured to identify a value of the input vector that none of the tied control store entries that are enabled by the entry-enables register arc configured to identify is enabled.

Claims20

Dependent claims

A system comprising:

a source bus;
a component connected to the source bus, wherein the component produces a first set of electrical signals;
a node controller, connected to the source bus, comprising control logic that receives the first set of electrical signals from the source bus as an input vector and produces an output vector comprising a second set of electrical signals, wherein the control logic comprises:
an entry-enables register that selectively enables and disables a plurality of control store entries that include:
a plurality of tied control store entries, wherein the tied control store entries each includes hard-coded logic configured to identify unique values of the input vector from the source bus and produces the second set of electrical signals from a hard-coded output vector when the input vector is identified and when the tied control store is enabled;
and
a plurality of spare control store entries, wherein the spare control store entries each includes programmable logic configurable to identify values of the input vector and produces the second set of electrical signals from a programmable output vector when the input vector is identified and when the spare control store is enabled,
wherein at least one of the spare control store entries is configured to identify a value of the input vector for which none of the tied control store entries that are enabled by the entry-enables register are configured to identify,
wherein the entry-enables register enables the at least one of the spare control store entries;
and
a destination bus that receives the output vector from the node controller, wherein the node controller is connected to the bus.

8 more elements

A method comprising:

receiving an input vector comprising a first set of electrical signals from a component of a source bus of a computing device;
identifying values of the input vector with at least one of a plurality of control store entries, wherein the plurality of control store entries includes a first subset comprising tied control store entries that each include hard-coded logic and hard-coded output vectors, and wherein the plurality of control store entries includes a second subset comprising spare control store entries that each include programmable logic and a programmable output vector;
receiving a signal that selectively enables and disables each of the tied control store entries and each of the spare control store entries, wherein the signal enables at least one of the spare control store entries that is configured to identify a value of the input vector for which none of the tied control store entries that are enabled by the signal are configured to identify;
and
outputting the programmable output vector of the at least one of the spare control store entries to a destination bus of the computing device.

2 more elements

A device comprising:

means for receiving an input vector comprising a first set of electrical signals from a component of a source bus of a computing device;
means for identifying values of the input vector with at least one of a plurality of control store entries, wherein the plurality of control store entries includes a first subset comprising tied control store entries that each include hard-coded logic and hard-coded output vectors, and wherein the plurality of control store entries includes a second subset comprising spare control store entries that each include programmable logic and a programmable output vector;
means for receiving a signal that selectively enables and disables each of the tied control store entries and each of the spare control store entries, wherein the signal enables at least one of the spare control store entries that is configured to identify a value of the input vector for which none of the tied control store entries that are enabled by the signal are configured to identify;
and
means for outputting the programmable output vector of the at least one of the spare control store entries to a destination bus of the computing device.

2 more elements

Dependencies are inferred from the claim text.