Method for composing on-chip network topology

A method of composing an on-chip network topology, the method comprising:

• analyzing a communications pattern between IP modules and generate a traffic graph by performing SoC designing specification-implemented reference codes and generating a traffic graph;
• generating a binary tree having the IP modules as the lowermost child nodes based on the traffic graph;
• obtaining a minimum solution of each node while sequentially searching the binary tree in a direction from the lowermost nodes to the uppermost node, and if a search target node has child nodes, obtaining a minimum solution of the search target node by using the minimum solutions of the child nodes;
• if the search target node is a root node, stopping the searching of the binary tree and merging the nodes of the binary tree according to the minimum solution of the search target node;
• inserting an additional path for shortening communications time between nodes into the binary tree to optimize the binary tree;
• and
• generating hardware having the optimized binary tree as an on-chip topology.