US 2010/0161750 A1 · IP STORAGE PROCESSOR AND ENGINE THEREFOR USING RDMA

Abstract

An IP Storage processor and processing engines for use in the IP storage processor is disclosed. The IP Storage processor uses an architecture that may provide capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also perform packet inspection through Layer 7. The engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache may store a transport protocol session information database and/or store a storage information session database, for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through ROMA data transfer.

Claims10

Dependent claims

1-63. (canceled)

A programmable TCP/IP chip used for processing Internet Protocol packets in TCP/IP sessions in accordance with TCP/IP session information and configured to be coupled to one or more host processors of a host system, said one or more host processors for processing data transferred using said internet Protocol Packets, said host system comprising host buffers coupled to said one or more host processors, said programmable TCP/IP chip comprising:

a. a remote direct memory access (RDMA) capability for performing RDMA data transfers;
b. at least one network interface configured to send and/or receive said Internet Protocol packets from or to said TCP/IP chip;
c. a memory on said TCP/IP chip for storing said TCP/IP session information or said Internet Protocol packets;
d. a memory controller for controlling access to said memory for storing or retrieving said TCP/IP session information or said Internet Protocol packets.
e. a TCP checksum generator for checksum generation or verification or a combination thereof;
f. a TCP segmentation controller for performing TCP segmentation;
g. a TCP/IP header processing engine for processing or generating TCP/IP headers or fields;
h. a RDMA header processing engine for generating or processing RDMA headers or fields;
i. a transmit engine or a receive engine or a combination thereof for retrieving data from said host buffers or performing direct data placement or zero copy in said host buffers without substantial intervention by said one or more host processors;
j. an execution resource to perform TCP/IP operations on said Internet Protocol packets;
k. an execution resource to perform RDMA operations on said Internet Protocol packets that require RDMA processing;
and
l. a host interface controller to couple said TCP/IP chip to said one or more host processors.

10 more elements

A programmable TCP/IP chip used for processing Internet Protocol packets and configured to be coupled to a host system, said host system comprising one or more host processors, said one or more host processors having access to host buffers, said TCP/IP chip comprising:

a. a memory for storing or retrieving said Internet Protocol Packets, or having access to a memory of said TCP/IP chip for storing or retrieving said Internet Protocol packets;
b. remote direct memory access (RDMA) capability for performing RDMA data transfers;
c. a RDMA engine for performing RDMA data transfers;
d. at least one network interface to send or receive said Internet Protocol packets;
e. a memory controller for controlling access to said memory on said TCP/IP chip or off said TCP/IP chip for storing or retrieving said Internet Protocol packets;
f. an execution resource to perform TCP/IP operations on said Internet Protocol packets comprising;
f1. a TCP checksum generator for checksum generation or verification or a combination thereof;
f2. a TCP segmentation controller for performing TCP segmentation;
f3. a TCP/IP header processing engine for processing or generating TCP/IP headers or fields;
and
f4. a combination of any of f1, f2, and f3;
g. a transmit engine or a receive engine or combination thereof for retrieving data from said host buffers or performing direct data placement or zero copy in said host buffers without substantial intervention by said one or more host processors;
and
h. a host interface controller configured to couple said TCP/IP chip to said one or more host processors.

11 more elements

Dependencies are inferred from the claim text.

Ip storage processor and engine therefor using rdma

Life of this patent

Ip storage processor and engine therefor using rdma

Life of this patent

Abstract

Claims10