System for determining median values of video data

A system for determining the median of a plurality of data values, the system comprising:

• a plurality of field programmable gate arrays (FPGA) including a plurality of configurable logic elements and a plurality of configurable storage elements;
• a plurality of inter FPGA links, each inter FPGA link included within one FPGA and configured to allow communication from one FGPA to another FPGA;
• an input router formed from the configurable logic elements and is configured to receive the plurality of data values and create a plurality of data streams, each data stream including a portion of the plurality of data values;
• a plurality of median modules formed from the configurable logic elements and the configurable storage elements and configured to receive at least one data stream, increment a plurality of counters, wherein each counter corresponds to a single data value within the range of data values, and determine the median by accumulating the contents of each counter;
• and
• a plurality of output transfer modules, each output transfer module included within one FPGA and configured to transfer the median to an external destination along with performance statistics of the determination of the median.

A system for determining the median of a plurality of data values, the system comprising:

• a plurality of field programmable gate arrays (FPGA) including a plurality of configurable logic elements and a plurality of configurable storage elements;
• a plurality of inter FPGA links, each inter FPGA link included within one FPGA and configured to allow communication from one FGPA to another FPGA;
• an input router formed from the configurable logic elements and is configured to receive the plurality of data values and create a plurality of data streams, each data stream including a portion of the plurality of data values;
• a plurality of median modules formed from the configurable logic elements and the configurable storage elements and configured to receive at least one data stream, and further including
• at least one dual-port memory element coupled to an adder, wherein the adder is configured to add one to the contents of each address of the at least one dual-port memory element,
• an address generator coupled to an address bus of the at least one dual-port memory element and configured to generate each address of the at least one dual-port memory element in sequential order;
• an accumulator coupled to a data bus of the at least one dual-port memory element and configured to accumulate the contents of each address of the at least one dual-port memory element in sequential order,
• a comparator configured to compare the contents of the accumulator with the total number of the plurality of data values divided by two and to generate a signal if the contents of the accumulator is greater than or equal to the total number of the plurality of data values divided by two, and
• an address register coupled to the comparator and configured to determine the median upon receipt of the signal from the comparator;
• and
• a plurality of output transfer modules, each output transfer module included within one FPGA and configured to transfer the median to an external destination along with performance statistics of the determination of the median.

A method for determining the median of a plurality of data values, the method comprising the steps of:

• a) establishing at least one dual-port memory element within a field programmable gate array (FPGA) wherein the at least one dual-port memory element includes an address that corresponds to each value in the range of data values;
• b) receiving all of the data values into the FPGA;
• c) counting the occurrence of each data value in the plurality of data values by incrementing the contents of the address that corresponds to the data value;
• d) sequentially accumulating the contents of each address of the at least one dual-port memory element utilizing an accumulator within the FPGA;
• e) comparing the contents of the accumulator after each address is accumulated with the total number of the plurality of data values divided by two utilizing a comparator within the FPGA;
• and
• f) generating the median as being the current address of the at least one dual-port memory element when the contents of the accumulator equals the total number of the plurality of data values divided by two.