Method of interconnect checking and verification for multiple electrostatic discharge specifications

A method for designing a semiconductor device component, comprising:

• specifying a set of semiconductor device component design criteria, wherein the set of semiconductor device component design criteria comprises at least one ESD model;
• prior to manufacturing the semiconductor device component, simulating an ESD event for the at least one ESD model on the semiconductor device component design;
• and
• verifying through simulation that the semiconductor device component design is resilient to the ESD event for the at least one ESD model.

A method for designing a semiconductor device circuit, comprising:

• designing a semiconductor device circuit comprising an electrostatic discharge (ESD) protection circuit;
• simulating a first ESD event using a first ESD model on the semiconductor device circuit;
• if the semiconductor device circuit fails during the first simulated ESD event:
• determining which semiconductor device circuit feature failed the first ESD event;
• selecting a device feature parameter for modification in response to failing the first ESD event;
• modifying the device feature parameter selected in response to failing the first ESD event;
• and
• again simulating the first ESD event on the semiconductor device circuit;
• after simulating the first ESD event, simulating a second ESD event using a second ESD model different than the first ESD model on the semiconductor device circuit;
• if the semiconductor device circuit fails during the second simulated ESD event:
• determining which semiconductor device circuit feature failed the second ESD event;
• selecting a device feature parameter for modification in response to failing the second ESD event;
• modifying the device feature parameter selected in response to failing the second ESD event;
• and
• again simulating the second ESD event on the semiconductor device circuit.