Semiconductor test apparatus and test method
AssigneeAdvantest Corporation
InventorMitsuo Matsumoto
Life of this patent
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Abstract
In a semiconductor test apparatus, a voltage source generates a power supply voltage to be supplied to a DUT. A decision processor makes the DUT execute a predetermined test sequence. A noise generator superimposes a periodic pulse-like noise voltage on the power supply voltage to be supplied to the DUT, while the test sequence is being executed. The noise generator superimposes a noise voltage synchronized with a clock signal to be supplied to the DUT.
Claims21
A semiconductor test apparatus comprising:
- a voltage source that generates a power supply voltage to be supplied to a device under test;
- a decision processor that makes the device under test execute a predetermined test sequence;
- and
- a noise generator that superimposes an impulse-like noise voltage on the power supply voltage to be supplied to the device under test, while the test sequence is being executed.
A semiconductor test apparatus comprising:
- a voltage source that generates a power supply voltage to be supplied to a device under test;
- a decision processor that makes the device under test execute a predetermined a test sequence;
- and
- a noise generator that superimposes a periodic pulse-like noise voltage on the power supply voltage to be supplied to the device under test, while the test sequence is being executed.
A semiconductor test method comprising:
- making a device under test execute a predetermined test sequence to determine pass or fail of the device under test;
- and
- superimposing an impulse-like noise voltage on a power supply voltage to be supplied to the device under test, while the test sequence is being executed.
A semiconductor test method comprising:
- making a device under test execute a predetermined test sequence to determine pass or fail of the device under test;
- and
- superimposing a periodic pulse-like noise voltage on a power supply voltage to be supplied to the device under test, while the test sequence is being executed.
A semiconductor test method comprising:
- generating a test pattern that can be distinguished by an address at every predetermined unit time;
- determining pass or fail of a device under test by using the test pattern in a state where a noise voltage synchronized with the unit time is superimposed on a power supply voltage to be supplied to the device under test;
- acquiring, when the device under test is determined as pass, the amplitude of the noise voltage as a pass voltage;
- acquiring, when the device under test is determined as fail, the amplitude of the noise voltage as a fail voltage;
- setting the amplitude of the noise voltage as the fail voltage with respect to at least one unit time of the test pattern, and setting that as the pass voltage with respect to a remaining unit time;
- and
- redetermining pass or fail of the device under test in a state where the noise voltage set in the setting is superimposed, wherein the setting the amplitude of the noise voltage and the redetermining pass or fail of the device under test are repeatedly executed.
Dependencies are inferred from the claim text.