Dll circuit
AssigneeHynix Semiconductor Inc.
InventorTae Kyun KIM
Life of this patent
Estimating the term…
Abstract
A delay locked loop (DLL) circuit includes a clock input buffer that generates a reference clock signal by buffering an external clock signal and outputs the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle control signal. The DLL circuit also includes a timing compensation unit configured that generates a compensation reference clock signal by compensating for a toggle timing of the reference clock signal that is changed during the duty cycle correction operation in response to a timing control signal. The DLL circuit further includes and a duty cycle control unit that generates the duty cycle control signal and the timing control signal by detecting the duty cycle of the reference clock signal.
Claims22
A delay locked loop (DLL) circuit comprising:
- a clock input buffer configured to generate a reference clock signal by buffering an external clock signal and to output the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle control signal;
- a timing compensation unit configured to generate a compensation reference clock signal by compensating for a toggle timing of the reference clock signal that is changed during a duty cycle correction operation in response to a timing control signal;
- and
- a duty cycle control unit configured to generate the duty cycle control signal and the timing control signal by detecting the duty cycle of the reference clock signal.
A delayed locked loop (DLL) circuit comprising:
- a buffer configured to output a buffered clock signal by correcting a duty cycle of a clock signal;
- a timing compensation unit configured to impart a negative delay time to the buffered clock signal when a high level interval of the buffered clock signal is greater than a low level interval of the buffered clock signal and to impart a positive delay time to the buffered clock signal when the high level interval of the buffered clock signal is less than the low level interval of the buffered clock signal;
- and
- a duty cycle control unit configured to control the operations of the buffer and the timing compensation unit by detecting the duty cycle of the buffered clock signal.
A delay locked loop circuit comprising:
- a duty cycle correction unit configured to generate a correction rising clock signal and a correction falling clock signal by performing a duty cycle correction operation on a rising clock signal and on a falling clock signal in response to a duty cycle control signal;
- a first timing compensation unit configured to compensate for a toggle timing of the correction rising clock signal that is changed during the duty cycle correction operation in response to a timing control signal;
- a second timing compensation unit configured to compensate for a toggle timing of the correction falling clock signal that is changed during the duty cycle correction operation in response to the timing control signal;
- and
- a duty cycle control unit configured to generate the duty cycle control signal and the timing control signal by detecting duty cycles of the correction rising clock signal and the correction falling clock signal.
Dependencies are inferred from the claim text.