Circuit device with serial bus isolation
AssigneeSilicon Laboratories Inc.
InventorLong V. Nguyen
Life of this patent
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Abstract
In a particular embodiment, a circuit device includes a first circuit having a first plurality of serial terminals including a first data receive terminal and a first data transmit terminal. The first plurality of serial terminals is communicatively coupled to a particular circuit via isolation circuitry to communicate first serial data. The circuit device further includes a second circuit having a second plurality of serial terminals including a second data receive terminal coupled to the first data transmit terminal and including a second data transmit terminal coupled to the first data receive terminal to communicate second serial data to the particular circuit via the first data receive and transmit terminals.
Claims21
A circuit device comprising:
- a first circuit comprising a first plurality of serial terminals including a first data receive terminal and a first data transmit terminal, the first plurality of serial terminals communicatively coupled to a particular circuit via isolation circuitry to communicate first serial data;
- and
- a second circuit comprising a second plurality of serial terminals including a second data receive terminal coupled to the first data transmit terminal and including a second data transmit terminal coupled to the first data receive terminal to communicate second serial data to the particular circuit via the first data receive and transmit terminals.
A subscriber line interface circuit (SLIC) device comprising:
- a pulse code modulation (PCM) circuit adapted to communicate voice data to a system, the PCM circuit comprising:
- a PCM frame synchronization terminal to receive a PCM frame synchronization signal from the system via a first isolated serial bus;
- a PCM clock terminal to receive a PCM clock signal from the system via a second isolated serial bus;
- a PCM data transmit terminal to transmit PCM data signals to the system via a third isolated serial bus;
- a PCM data receive terminal to receive PCM data signals from the system via a fourth isolated serial bus;
- and
- a serial peripheral interface (SPI) circuit adapted to communicate control data to the system via the third and fourth isolated serial buses, the SPI circuit comprising:
- an SPI chip select terminal to receive an SPI chip enable signal to selectively activate the SPI circuit;
- an SPI data output terminal coupled to the fourth isolated serial bus;
- and
- an SPI data input terminal coupled to the third isolated serial bus.
A circuit device comprising:
- a first circuit including a first plurality of terminals adapted to couple to a respective plurality of serial buses to communicate first serial data via isolation circuitry to a system, the first plurality of terminals comprising:
- a first serial data transmit terminal adapted to couple to a first data bus of the respective plurality of data buses;
- a first serial data receive terminal adapted to couple to a second data bus of the respective plurality of data buses;
- a first synchronization terminal adapted to couple to a first synchronization bus of the respective plurality of data buses;
- and
- a second circuit to selectively communicate second serial data via the first serial data receive and transmit terminals in response to receiving the chip select signal, the second circuit comprising:
- a second data receive terminal coupled to the first serial data transmit terminal;
- a second data transmit terminal coupled to the first serial data receive terminal;
- and
- a chip select terminal to receive a chip select signal to enable the second circuit to communicate the second serial data to the system.
Dependencies are inferred from the claim text.