Shift register with pre-pull-down module to suppress a spike

A shift register comprising:

• a plurality of cascade-connected stages, each stage for outputting an output pulse at an output end based on a first clock signal, a second signal, and a driving signal pulse from the previous one stage, each stage comprising:
• a pull-up module coupled to a first node, for providing the output pulse based on the first clock signal;
• a pull-up driving module coupled to the first node for switching on the pull-up module in response to the driving signal pulse from the previous one stage;
• a pre-pull-down module comprising a first end coupled to the first node, a second end coupled to an output end of previous two stage, and a third end coupled to a supply voltage end to receive a supply voltage, the pre-pull-down circuit for adjusting a voltage level of the first node to the supply voltage in response to an output pulse from the previous two stage;
• a pull-down module coupled to the first node for pulling down the voltage level of the first node to the supply voltage based on a pull-down driving signal;
• and
• a pull-down driving module for providing a pull-down triggering signal.