US 2010/0150290 A1 · Clock-Data Recovery ("CDR") Circuit, Apparatus And Method For Variable Frequency Data

Abstract

A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the clock circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the clock circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.

Claims23

Dependent claims

1) A circuit capable of tracking a data signal, comprising:

a clock circuit to generate at least one clock signal;
a sampler circuit to sample the data signal in response to the at least one clock signal to produce a series of data samples and a series of edge samples, the data signal having a variable data bit rate;
a phase detector to generate a phase movement signal in each of a plurality of adjustment cycles based on M data samples and N edge samples, wherein M and N are positive integers each larger than one;
and
logic circuitry to determine a phase drift of the data signal with respect to the at least one clock signal based on a plurality of phase movement signals output by the phase detector over a period of time that includes multiple adjustment cycles;
and
wherein the clock circuit is configured to adjust the at least one clock signal to track the data signal in response to a phase adjust signal derived from the phase movement signal and the phase drift.

4 more elements

Dependencies are inferred from the claim text.

Clock-Data Recovery ("CDR") Circuit, Apparatus And Method For Variable Frequency Data

Life of this patent

Clock-Data Recovery ("CDR") Circuit, Apparatus And Method For Variable Frequency Data

Life of this patent

Abstract

Claims23