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US 2010/0150270 A1Published application
Signal processing circuit and receiver using the same
AssigneeKabushiki Kaisha Toshiba
InventorsMasanori Furuta, Takafumi Yamaji
Life of this patent
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Abstract
A signal processing circuit includes a decimation filter which down-samples over-sampled first three-phase digital signals to obtain second three-phase digital signals, and a converter which subjects the second three-phase digital signals to a three-phase to IQ conversion, and obtains orthogonal digital signals.
Claims10
A signal processing circuit comprising:
- a decimation filter which down-samples over-sampled first three-phase digital signals to obtain second three-phase digital signals;
- and
- a converter which subjects the second three-phase digital signals to a three-phase to IQ conversion, and obtains orthogonal digital signals.
A signal processing circuit comprising:
- a first decimation filter which down-samples over-sampled first three-phase digital signals to obtain second three-phase digital signals;
- a converter which subjects the second three-phase digital signals to a three-phase to IQ conversion and obtains first orthogonal digital signals;
- and
- a second decimation filter which down-samples the first orthogonal digital signal to obtain second orthogonal digital signals.
1 more element
Dependencies are inferred from the claim text.