Method and system for hsdpa bit level processor engine

A method for processing signals in a communication system, the method comprising:

• pipelining processing of a received HSDPA bitstream within a single chip, wherein said pipelining comprises:
• calculating a memory address for a current portion of a plurality of information bits in said received HSDPA bitstream, while storing on-chip, a portion of said plurality of information bits in said received HSDPA bitstream that is subsequent to said current portion;
• and
• decoding during said calculating and storing, a portion of said plurality of information bits in said received HSDPA bitstream that is previous to said current portion.

A machine-readable storage having stored thereon, a computer program having at least one code section for processing signals in a communication system, the at least one code section being executable by a machine for causing the machine to perform steps comprising:

• pipelining processing of a received HSDPA bitstream within a single chip, wherein said pipelining comprises:
• calculating a memory address for a current portion of a plurality of information bits in said received HSDPA bitstream, while storing on-chip, a portion of said plurality of information bits in said received HSDPA bitstream that is subsequent to said current portion;
• and
• decoding during said calculating and storing, a portion of said plurality of information bits in said received HSDPA bitstream that is previous to said current portion.

A system for processing signals in a communication system, the system comprising:

• circuitry that enables pipelining processing of a received HSDPA bitstream within a single chip, wherein said circuitry that enables said pipelining comprises:
• one or more circuits that enables calculation of a memory address for a current portion of a plurality of information bits in said received HSDPA bitstream;
• said one or more circuits enables storing on-chip of a portion of said plurality of information bits in said received HSDPA bitstream that is subsequent to said current portion;
• and
• said one or more circuits enables decoding during said calculating and said storing of a portion of said plurality of information bits in said received HSDPA bitstream that is previous to said current portion.