Semiconductor memory device that can relief defective address
AssigneeElpida Memory, Inc.
InventorsNoriaki Mochida, Kyoichi Nagata
Life of this patent
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Abstract
To comprise a memory cell array, a read amplifier that is provided outside the memory cell array and amplifies data read from the memory cell array, a write amplifier that is provided outside the memory cell array and amplifies data to be written in the memory cell array, and a relief storage cell that is provided outside the memory cell array and connected to an input terminal of the read amplifier and an output terminal of the write amplifier via a switch. With this configuration, a timing of operating a main amplifier and the relief storage cell does not need to be changed depending on a position of a memory block. Further, the number of components required for connecting to the relief storage cell can be minimized.
Claims20
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells and a plurality of sense amplifiers that performs data communication with the memory cells;
- a read amplifier that is provided outside the memory cell array and amplifies data read from one of the memory cells via one of the sense amplifiers;
- a write amplifier that is provided outside the memory cell array and amplifies data to be written in one of the memory cells via one of the sense amplifiers;
- and
- a relief storage cell that is provided outside the memory cell array and connected to an input terminal of the read amplifier and an output terminal of the write amplifier via a first switch.
A semiconductor memory device comprising:
- a plurality of memory cells;
- a plurality of sense amplifiers each connected to any of the memory cells;
- a plurality of first data buses each connected to any of the sense amplifiers via respective column switches;
- a plurality of second data buses each connected to any of the first data buses via respective sub-amplifiers;
- a plurality of main amplifiers each connected to an associated one of the second data buses and amplify data on the second data bus;
- a plurality of relief storage cells each connected to an associated one of the second data buses via respective relief switches;
- and
- an address comparison circuit that turns on the relief switches in response to an access request to a predetermined address including an X address and a Y address.
A semiconductor memory device comprising:
- a plurality of memory cells;
- a plurality of sense amplifiers each connected to any of the memory cells;
- a hierarchized data bus that performs data communication with the memory cells, the hierarchized data bus including at least a first data bus assigned to a first hierarchized layer and a second data bus assigned to a second hierarchized layer;
- a memory cell array including the memory cells, the sense amplifiers, and the first hierarchized data bus and the second hierarchized data bus;
- a read amplifier that is arranged outside the memory cell array and receives an output signal of the sense amplifiers via the first and second hierarchized data buses;
- a relief storage cell that is arranged outside the memory cell array and connected to an input terminal of the read amplifier via a relief switch;
- and
- an address comparison circuit that turns on the relief switch in response to an access request to a predetermined address including an X address and a Y address, wherein
- a line-and-space value (L/S) for a transistor, a wiring, and a contact of the relief storage cell is larger than a line-and-space value (L/S) for a transistor, a wiring, and a contact of the sense amplifier.
Dependencies are inferred from the claim text.