System with controller and memory
AssigneeElpida Memory, Inc.
InventorAtsuo KOSHIZUKA
Life of this patent
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Abstract
According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.
Claims18
A controller comprising a first terminal, a second terminal and a third terminal, the controller being adapted to produce a first signal at the first terminal and a write data signal at the third terminal in a write operation, the write data signal being synchronized with the first signal, the controller being adapted to produce a second signal at the first terminal and to receive a read data at the third terminal in synchronization with a third signal arriving at the second terminal from outside of the controller in a read operation.
A controller comprising:
- first, second, third, fourth and fifth terminals;
- a clock generator supplied with a clock signal, generating a first signal based on the clock signal, outputting the first signal to the first terminal, generating a second signal based on the clock signal, and outputting the second signal to the second terminal;
- a command control circuit generating a command signal in synchronization with the first signal, and outputting the command signal to the third terminal;
- and
- a data control circuit generating a first data signal in synchronization with the second signal, and outputting the first data signal to the fourth terminal, receiving a second data signal at the fourth terminal in synchronization with a third signal arriving at the fifth terminal from outside of the controller, and the third signal being arrived at the fifth terminal in response to the outputting the second signal to the second terminal.
A. controller comprising first, second and third terminals provided independently of each other, the controller being adapted to generate a write data signal at the third terminal while the controller is clocking the first terminal, the controller being adapted to receive a read data signal at the third terminal while the second terminal is being clocked from an outside of the controller and while the controller is clocking the first terminal.
Dependencies are inferred from the claim text.