Semiconductor memory device and method for operating the same

Abstract

In example embodiments, the semiconductor memory device, and the method for operating the semiconductor memory device, includes a memory cell array having a plurality of memory cells each formed of a transistor having a floating body. The transistors are coupled between a plurality of word lines, a plurality of source lines and a plurality of bit lines. Additionally, the memory cell array includes a controller configured to read data from at least one of the memory cells and restore data to the memory cell storing a first data state through a bit operation of the memory cell. The controller restores data to the memory cell by applying a first source-line control voltage to a selected source line and applying a first word-line control voltage to a selected word line in a first period of a read operation. Also, the controller is configured to restore data to the memory cell, which is storing a second data state, by applying a second source-line control voltage to the selected source line and applying a second word-line control voltage to the selected word line in a second period of the read operation.

Dependencies are inferred from the claim text.