Reduction of power consumption in a memory device during sleep mode of operation

Abstract

The present disclosure relates to a system comprising memory device with a power switch where the system comprises a first voltage controlled switch coupling positive power supply to positive supply terminal of memory device core; a second voltage controlled switch coupling negative power supply to negative supply terminal of the memory device core; a first reference voltage coupled to the substrate terminal of said first voltage controlled switch; and a second reference voltage coupled to the substrate terminal of said second voltage controlled switch. This helps maintain a sufficient RNM for efficient performance by the system.

Dependencies are inferred from the claim text.