Methods of Operating Embedded Flash Memory Devices
AssigneeInfineon Technologies AG
InventorsDanny Pak-Chum Shum, Armin Tilke, Jiang Yan
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Abstract
Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices.
Claims20
A method of operating a flash memory array, the flash memory array having flash memory cells arranged in rows and columns, each flash memory cell having a body and each column of flash memory cells being formed in a continuous region of semiconductor that overlies a buried insulator, each column being separated from adjacent columns of flash memory cells by an isolation region, the method comprising:
- selecting a flash memory cell in one of the columns;
- applying a first voltage to the body of each flash memory cell in the one of the columns;
- applying a second voltage to the body of each flash memory cell in a column that is immediately adjacent to the one of the columns;
- and
- accessing the selected flash memory cell.
A method of writing a flash memory array, the flash memory array having flash memory cells arranged in rows and columns, each flash memory cell having a body and each column of flash memory cells being formed in a continuous region of semiconductor that overlies a buried insulator, each column being separated from adjacent columns of flash memory cells by an isolation region, the method comprising:
- selecting a flash memory cell in a first column of flash memory cells;
- latching the bodies of the first column of flash memory cells;
- applying a first voltage to the bodies of the first column of flash memory cells;
- applying a second voltage to the bodies of each column of flash memory cells that is immediately adjacent to the first column of flash memory cells;
- and
- writing the selected flash memory cell.
The method of claim 16, wherein the flash memory array comprises input/output transistors having a dual gate oxide.
A method of erasing a flash memory array, the flash memory array having flash memory cells arranged in rows and columns, each flash memory cell having a body and each column of flash memory cells being formed in a continuous region of semiconductor that overlies a buried insulator, each column being separated from adjacent columns of flash memory cells by an isolation region, the method comprising:
- selecting a flash memory cell in a first column of flash memory cells;
- latching the bodies of the first column of flash memory cells;
- applying a first voltage to the bodies of the first column of flash memory cells;
- applying a second voltage to the bodies of each column of flash memory cells that is immediately adjacent to the first column of flash memory cells;
- and
- erasing the selected flash memory cell.
Dependencies are inferred from the claim text.