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US 2010/0149880 A1Published application
Window enlargement by selective erase of non-volatile memory cells
AssigneeMacronix International Co., Ltd.
InventorsPo Chou Chen, I Chen Yang, Hui Chih Lin, Yao Wen Chang
Life of this patent
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Abstract
A method is described for enlarging a programming window of charge trapping memory cells in a virtual ground charge trapping memory EEPROM array. The method substantially eliminates second bit effects and program disturbances to nearby charge trapping memory cells.
Claims23
A method, comprising:
- providing an array of charge trapping memory cells, the array comprising a plurality of rows of charge trapping memory cells;
- identifying a row of the array;
- identifying a first charge trapping memory cell in the identified row, the first charge trapping memory cell having first and second data regions;
- receiving a first programming instruction according to the first and second data regions in the first charge trapping memory cell;
- programming the first data region in the first charge trapping memory cell when the first programming instruction dictates programming of the first data region in the first charge trapping memory cell;
- and
- erasing the second data region in the first charge trapping memory cell when the first programming instruction dictates programming of the first data region in the first charge trapping memory cell and when the first programming instruction does not dictate programming of the second data region in the first charge trapping memory cell.
4 more elements
A method, comprising:
- providing an array comprising a plurality of rows of charge trapping memory cells;
- identifying a row of the array;
- identifying a first charge trapping memory cell in the identified row, the first charge trapping memory cell having first and second data regions;
- identifying a second charge trapping memory cell in the identified row, the second charge trapping memory cell having a first data region that shares a bitline with the second data region of the first charge trapping memory cell;
- receiving a first programming instruction according to the first and second data regions in the first charge trapping memory cell;
- receiving a second programming instruction according to the first data region of the second charge trapping memory cell;
- programming the second data region in the first charge trapping memory cell when the first programming instruction dictates programming of the second data region in the first charge trapping memory cell;
- and
- erasing the first data region in the second charge trapping memory cell when the first programming instruction dictates programming of the second data region in the first charge trapping memory cell and when the second programming instruction does not dictate programming of the first data region in the second charge trapping memory cell.
6 more elements
A nonvolatile memory composed of an array of rows and columns of cells, each cell comprising:
- a substrate region including source and drain regions to which bitlines are connected, the bitlines being shared by cells in a column of the array;
- a charge storage structure having first and second data regions;
- and
- one or more dielectric structures disposed at least partly between the charge storage structure and the substrate region and at least partly between the charge storage structure and a gate connection, the gate connection being connected to a word line, the word line being shared by cells in a row of the array, wherein an operating window of the cell is increased by selectively erasing the first data region that is to remain erased when the second data region is to be programmed.
1 more element
Dependencies are inferred from the claim text.