Push-pull fpga cell

A flash memory array arranged in rows and columns of memory cells and including:

• a p-channel column line for each column in the array;
• an n-channel column line for each column in the array;
• a p-channel row line for each row in the array;
• an n-channel row line for each row in the array;
• an assist row line for each row in the array;
• a plurality of memory cells, each memory cell associated with a row and a column in the array and including a p-channel flash transistor having a source coupled to the p-channel column line of the column containing the memory cell, a drain, a floating gate, and a control gate coupled to the p-channel row line of the row containing the memory cell, an n-channel flash transistor having a source coupled to the n-channel column line of the column containing the memory cell, a drain connected to the drain of the p-channel flash transistor, a floating gate, and a control gate coupled to the n-channel row line of the row containing the memory cell, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate coupled to the assist row line of the row containing the memory cell.

A flash memory array arranged in rows and columns of memory cells and including:

• a p-channel column line for each column in the array;
• an n-channel column line for each column in the array;
• a fish row line for each row in the array;
• an assist row line for each row in the array;
• a plurality of memory cells, each memory cell associated with a row and a column in the array and including a p-channel flash transistor having a source coupled to the p-channel column line of the column containing the memory cell, a drain, a floating gate, and a control gate coupled to the flash row line of the row containing the memory cell, an n-channel flash transistor having a source coupled to the n-channel column line of the column containing the memory cell, a drain connected to the drain of the p-channel flash transistor, a floating gate common with the floating gate of the p-channel flash transistor, and a control gate coupled to the flash row line of the row containing the memory cell, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate coupled to the assist row line of the row containing the memory cell.