Back to results
US 2010/0149866 A1Published application
Systems and Devices Including Memory Resistant to Program Disturb and Methods of Using, Making, and Operating the Same
AssigneeMicron Technology, Inc.
InventorSatoru Tamada
Life of this patent
Estimating the term…
Abstract
Disclosed are methods, systems and devices, one such device being a memory device configured to concurrently assert a first pulse pattern through a plurality of conductors disposed on both a source side and a drain side of a floating-gate transistor, wherein a source side of the first pulse pattern has a different median voltage than a drain side of the first pulse pattern.
Claims21
A device, comprising:
- a memory array comprising floating-gate transistors, wherein respective pluralities of the floating-gate transistors have commonly-coupled control gates;
- and
- a driver configured to enable a selected one of the floating-gate transistors to be programmed, wherein the driver is configured to assert a first pulse pattern and a second pulse pattern on the control gates of the floating-gate transistors, wherein voltages of pulses of the first pulse pattern asserted on control gates of a first group of pluralities of the floating-gate transistors on a source side of the selected one of the floating gate transistors are higher than voltages of the first pulse pattern asserted on control gates of a second group of pluralities of the floating-gate transistors on a drain side of the selected one of the floating-gate transistors.
A method of programming a selected memory cell, the method comprising:
- asserting a first inhibit voltage on a first side of the selected memory cell;
- asserting a second inhibit voltage on a second side of the selected memory cell;
- asserting a programming voltage on the selected memory cell;
- asserting a first pass voltage on memory cells on the first side of the selected memory cell;
- and
- asserting a second pass voltage on memory cells on the second side of the selected memory cell.
3 more elements
A memory device comprising:
- memory cells;
- and
- a driver configured to concurrently assert a first pulse pattern and a second pulse pattern on the memory cells, wherein the first pulse pattern comprises a first voltage on a plurality of memory cells on a first side of a selected one of the memory cells and a second voltage on a plurality of memory cells on a second side of the selected one of the memory cells, wherein the second pulse pattern comprises a third voltage on another plurality of memory cells on the first side of the selected one of the memory cells and a fourth voltage on another plurality of memory cells on the second side of the selected one of the memory cells, wherein the first voltage is higher than the second voltage and the third voltage is lower than the fourth voltage.
Dependencies are inferred from the claim text.