Memory circuit with quantum well-type carrier storage
AssigneeThe Board of Trustees of the Leland Stanford Junior University
InventorsMehmet Günhan Ertosun, Krishna Chandra Saraswat, Pawan Kapur
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Abstract
Data is stored in a quantum-well type structure with double gate control. According to an example embodiment, a transistor-based data storage circuit includes a gate, a back gate and a semiconductor channel between the gate and the back gate. Carriers are stored in a storage pocket structure in the channel, in response to biases applied to the gate and back gate. Current passing through the channel is sensed and used to detect the stored carriers and, correspondingly, a memory state of the storage circuit.
Claims22
A transistor-based data storage circuit comprising:
- a gate;
- a back gate;
- and
- a semiconductor channel between the gate and the back gate and having a storage pocket structure that is configured to store carriers for storing data in response to a bias applied to the gate and another bias applied to the back gate, and to pass current for detecting a memory state of the storage circuit that is responsive to the stored carriers.
A capacitorless transistor memory circuit arrangement comprising:
- a gate;
- a back gate;
- a gate insulator material in contact with the gate;
- a back gate insulator material in contact with the back gate;
- a source;
- a drain;
- and
- a semiconductor channel between the gate insulator material and the back gate insulator material, the channel including, at a region separated from and between each of the gate and back gate, a quantum well-type region that is configured and arranged to store carriers in response to a bias applied to the gate and another bias applied to the back gate;
- wherein the semiconductor channel exhibits a detectable logic state that is defined as a function of conductivity of the channel between the source and drain as set by the stored carriers.
A method for storing, reading and erasing data from a transistor-based data storage circuit having a gate, a back gate and a semiconductor channel between the gate and the back gate, the semiconductor channel having a storage pocket structure that is configured to store carriers indicative of a memory state of the transistor-based data storage circuit, the method comprising:
- applying a front bias to the gate and applying back bias to the back gate to store carriers in the storage pocket structure to set the memory state of the transistor-based data storage circuit;
- sensing current passing through the semiconductor channel to detect the memory state of the transistor-based data storage circuit;
- and
- applying an erasing bias to purge carriers from the storage pocket structure.
Dependencies are inferred from the claim text.