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US 2010/0149849 A1Published application
Memory array on more than one die
AssigneeIntel Corporation
InventorsMohammed Taufique, Derwin Jallice, Donald W. McCauley, John P. DeVale, Edward A. Brekelbaum, Jeffrey P. Rupley, II, Gabriel H. Loh, Bryan Black
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Abstract
For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
Claims22
An apparatus comprising:
- a first die including a first plurality of memory cells for a memory array;
- and
- a second die including a second plurality of memory cells for the memory array, the second die including a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells.
A method comprising:
- selecting one or more memory cells of a memory array having a first plurality of memory cells on a first die and a second plurality of memory cells on a second die, wherein the second die includes a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells;
- and
- accessing one or more selected memory cells of the memory array.
A system comprising:
- a processor;
- memory circuitry including a memory array having a first plurality of memory cells on a first die and a second plurality of memory cells on a second die, wherein the second die includes a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells;
- and
- volatile memory.
1 more element
Dependencies are inferred from the claim text.