Liquid crystal display and method of driving the same
AssigneeLG Display Co., Ltd.
InventorsJincheol Hong, Pilsung Kang, Mangyu Park, Geunwoo Koh
Life of this patent
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Abstract
A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, and a feedback lock check line that connects a last source drive IC of the N source drive ICs to the timing controller.
Claims20
A liquid crystal display comprising:
- a timing controller;
- N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2;
- N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner;
- a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another;
- and
- a feedback lock check line that connects a last source drive IC of the N source drive ICs to the timing controller,
- wherein the timing controller serially transfers a preamble signal, in which a plurality of bits having a high logic level are successively arranged and then a plurality of bits having a low logic level are successively arranged, to each of the N source drive ICs through each of the N pairs of data bus lines, transfers a lock signal indicating that a phase of an internal clock pulse output from each of the N source drive ICs is locked to the first source drive IC through the lock check line, receives a feedback signal of the lock signal from the last source drive IC through the feedback lock check line, and serially transfers at least one source control packet for controlling a data voltage output from each of the N source drive ICs to each of the N source drive ICs through each of the N pairs of data bus lines.
A method of driving a liquid crystal display including a timing controller and N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, the method comprising:
- generating a preamble signal, in which a plurality of bits having a high logic level are successively arranged and then a plurality of bits having a low logic level are successively arranged, from the timing controller;
- transferring the preamble signal serially to each of the N source drive ICs through each of N pairs of data bus lines connecting the timing controller to the N source drive ICs in a point-to-point manner;
- generating a lock signal indicating that a phase of an internal clock pulse output from each of the N source drive ICs is locked from the timing controller;
- transferring the lock signal to a first source drive IC of the N source drive ICs through a lock check line that connects the first source drive IC to the timing controller and cascade-connects the N source drive ICs to one another;
- generating a feedback signal of the lock signal from a last source drive IC of the N source drive ICs;
- transferring the feedback signal of the lock signal to the timing controller through a feedback lock check line connecting the last source drive IC to the timing controller;
- generating at least one source control packet for controlling a data voltage output from each of the N source drive ICs from the timing controller;
- and
- transferring the source control packet serially to each of the N source drive ICs through each of the N pairs of data bus lines.
Dependencies are inferred from the claim text.