Liquid crystal display panel and electronic device

An electronic device, comprising:

• a liquid crystal display panel;
• a system control section controlling whole of the electric device;
• and
• an input operation section performing input operation to the system control section,
• the liquid crystal display panel including:
• a capacitive element holding pixel potential representing a gray-scale level and provided in each of pixels;
• a first switch element having a first terminal connected to one electrode of the capacitive element and to a drive electrode in a liquid crystal element, and having a second terminal connected to a signal line, the first switch element being controlled to be ON during a first operation period where pixel potential is written from the signal line to the capacitive element, and controlled to be OFF during a second operation period where readout of the pixel potential from the capacitive element, inversion and amplification of the read out pixel potential, and rewriting of the inverted-amplified pixel potential to the capacitive element are sequentially performed;
• a second switch element having a first terminal connected to a first terminal of the first switch element, the second switch element being controlled to be OFF during the first operation period, and controlled to be ON during a readout period where pixel potential stored in the capacitive element is read out, the readout period being one part of the second operation period;
• a third switch element having a first terminal connected to the first terminal of the first switch element, the third switch element being controlled to be OFF during the first operation period, and controlled to be ON during a write period where the pixel potential is written into the capacitive element, the write period being another part of the second operation period;
• and
• a circuit restoring a logic level of pixel potential read out from the capacitive element through the second switch element during the readout period, and then writing logically-inverted output having the restored logic level to the capacitive element through the third switch element during the write period.