Duty control buffer circuit and duty correction circuit
AssigneeNEC Electronics Corporation
InventorSeiichi Watarai
Life of this patent
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Abstract
The circuit includes a duty control buffer and a duty control voltage generator that receives outputs of the duty control buffer, detects a duty error, and generates control signals. The duty control buffer includes a differential stage including unbalanced first and second differential pairs each differentially receiving input signals, a load element pair connected between output pairs of the first and second differential pairs and a power supply, and a current source stage that supplies respective driving currents to the first and second differential pairs.
Claims20
A duty control buffer circuit comprising:
- a first differential circuit that differentially receives input signals and generates first differential output signals comprising a non-inverting output signal and an inverting output signal, the first differential output signals making a transition responsive to a transition of the input signals, the first differential output signals having a predetermined magnitude relationship between a time of at least one of falling and rising transitions of the non-inverting output signal thereof and a time of the one of falling and rising transitions of the inverting output signal thereof;
- and
- a second differential circuit that differentially receives the input signals in common with the first differential circuit and generates second differential output signals comprising a non-inverting output signal and an inverting output signal, the second differential output signals making a transition responsive to a transition of the input signals, the second differential output signals having a magnitude relationship between a time of the one of falling and rising transitions of the non-inverting output signal thereof and a time of the one of falling and rising transitions of the inverting output signal thereof, the magnitude relationship of the second differential output signals being opposite to the magnitude relationship of the first differential output signals,
- a signal obtained by combining the non-inverting output signals of the first and second differential output signals and a signal obtained by combining the inverting output signals of the first and second differential output signals being produced respectively at first and second output terminals of the duty control buffer circuit.
A duty correction circuit comprising:
- a duty control buffer that receives input signals,
- the duty control buffer comprising:
- first and second differential pairs that differentially receive the input signals in common, current driving capabilities of output pairs of the first and second differential pairs being unbalanced,
- first outputs of the output pairs of the first and second differential pairs being connected together and second outputs of the output pairs of the first and second differential pairs being connected together;
- a duty correction voltage generator that receives outputs of the duty control buffer, the duty correction voltage generator detects a duty error to generate differentially control signals;
- a load element pair connected between a power supply and the commonly connected output pairs of the first and second differential pairs;
- and
- a current source stage that respectively supplies to the first and second differential pair driving currents corresponding to the control signals.
Dependencies are inferred from the claim text.