US 2010/0148833 A1 · DOMAIN CROSSING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS

Abstract

The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.

Claims21

Dependent claims

A domain crossing circuit of a semiconductor memory apparatus, comprising:

a sampler providing a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and providing an edge information signal defining an output timing of the sampling internal signal;
and
an output stage synchronizing the sampling internal signal with the clock in response to the edge information signal and outputting the synchronized sampling internal signal as a final output signal.

A domain crossing circuit of a semiconductor memory apparatus, comprising:

a sampler providing a sampling internal signal generated by synchronizing an internal input signal with a clock and an edge information signal that becomes an output reference of the sampling internal signal, wherein the internal input signal is a non-synchronous signal;
and
an output state in which a final output signal is synchronized with the clock by delaying the sampling internal signal at a different delay time according to levels of the edge information signal,
wherein the sampling internal signal is selectively synchronized with one of a rising edge and a falling edge of the clock and the final output signal is synchronized with the rising edge of the clock.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

12/486,281Filed 17 Jun 2009

Priority

KR 10-2008-012644712 Dec 2008

Published

17 Jun 2010

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

H04L 7/0338
Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals: the correction…
G11C 7/1078
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data input circuits, e.g. write amplifiers, data…
G11C 7/1087
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: data input latches
G11C 7/1093
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: input synchronization

Domain crossing circuit of a semiconductor memory apparatus

Life of this patent

Domain crossing circuit of a semiconductor memory apparatus

Life of this patent

Abstract

Claims21