Clock data recovery circuit
AssigneeNEC Electronics Corporation
InventorYoshinobu Oshima
Life of this patent
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Abstract
A simple circuit that supports high and low data rates is provided. The circuit includes: a detection circuit 11 for detecting whether D1≠D2 or D1≠D3, assuming that logical values of an input data signal DATAIN sampled at timings t1, t2, and t3 (t2<t1<t3) of edges of clock signals CLK0 and CLK1 are D1, D2, and D3, respectively; and a clock generation circuit 14 for changing phases of the clock signals CLK0 and CLK1 based on detection results from the detection circuit 11, so that timings at which the logical values of the input data signal DATAIN change correspond to the timings t2 and t3.
Claims5
A clock data recovery circuit comprising:
- a detection circuit that detects whether D1≠D2 and D1≠D3, provided that logical values of an input data signal sampled at timings t1, t2, and t3 where t2<t1<t3 of edges of a clock signal are D1, D2 and D3, respectively;
- and
- a clock generation circuit that changes phase of the clock signal based on detection results from the detection circuit, so that timings at which the logical values of the input data signal change correspond to the timings t2 and t3.
Dependencies are inferred from the claim text.