Semiconductor device
AssigneeMitsubishi Electric Corporation
InventorKazuhiro Shimizu
Life of this patent
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Abstract
An RESURF region is formed so as to surround a high-potential logic region with an isolation region interposed therebetween, in which a sense resistance and a first logic circuit which are applied with a high potential are formed in high-potential logic region. On the outside of RESURF region, a second logic circuit region is formed, which is applied with the driving voltage level required for driving a second logic circuit with respect to the ground potential. In RESURF region, a drain electrode of a field-effect transistor is formed along the inner periphery, and a source electrode is formed along the outer periphery. Furthermore, a polysilicon resistance connected to sense resistance is formed in the shape of a spiral from the inner peripheral side toward the outer peripheral side.
Claims8
A semiconductor device comprising:
- a first logic circuit region formed on a main surface of a first conductivity type semiconductor substrate, including a first resistance and a first logic circuit operating with a first driving voltage to control an operation of a predetermined switching element, and applied with a first voltage as a bias voltage;
- an annular region annularly formed on the main surface of said semiconductor substrate to circumferentially surround said first logic circuit region and including a field-effect transistor and a second resistance which are electrically connected to said first resistance;
- an isolation region formed between said first logic circuit region and said annular region, and providing electrical isolation between said first logic circuit region and said annular region;
- and
- a second logic circuit region formed on the main surface of said semiconductor substrate located outside said annular region, including a second logic circuit electrically connected to said field-effect transistor and said second resistance to operate with a second driving voltage, and applied with a second voltage as a bias voltage lower than said first voltage,
- said first logic circuit for controlling the operation of said switching element based on a predetermined potential difference caused by a drain current flowing through said first resistance when said field-effect transistor is turned on,
- said second logic circuit for detecting a current flowing through said second resistance to thereby determine a gate voltage to be applied to a gate of said field-effect transistor in order to cause a constant current to flow as said drain current, and apply said gate voltage to said gate,
- said annular region electrically isolating a drain of said field-effect transistor applied with said first voltage with respect to said second logic circuit region, and
- said isolation region electrically isolating said first logic circuit region at least by said first driving voltage with respect to the drain of said field-effect transistor which is applied with said first voltage.
Dependencies are inferred from the claim text.