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US 2010/0148818 A1Published application
High speed conditional back bias virtual ground restoration circuit
AssigneeMicrochip Technology Incorporated
InventorsNeil Deutscher, Jinhui Chen, Marquis Jones
Life of this patent
Estimating the term…
Abstract
A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage domains. Sneak current is caused when a signal between the two or more logic circuit modules in different voltage domains is at logic “0” and one of the logic circuit modules is biased at a voltage level above the true ground, VSS, of the integrated circuit device. The conditional ground restoration circuit shifts the virtual ground logic “0” to the true ground level. This eliminates sneak current and logic level corruption.
Claims19
An integrated circuit device having conditional back bias virtual ground restoration circuits for preventing sneak leakage currents and shifting a virtual ground level logic “0” to a true ground level logic “0” when logic “0” signals at the virtual ground level are applied in the integrated circuit device, comprising:
- at least one independent voltage domain operating at a virtual ground and at least one other independent voltage domain operating at a true ground, wherein the virtual ground is at a more positive voltage than the true ground;
- a plurality of conditional back bias virtual ground restoration circuits, each of the plurality of conditional back bias virtual ground restoration circuits is coupled between one of a plurality of first logic circuits operating in the virtual ground voltage domain and one of a plurality of second logic circuit operating in the true ground voltage domain, wherein the plurality of first and second logic circuits operating in the virtual and true ground voltage domains, respectively, are fabricated on an integrated circuit die, and
- wherein each of the plurality of ground restoration circuits comprises:
- a level shifter circuit having a logic input and a logic output, wherein the logic output follows logic levels at the logic input;
- and
- a switch transistor having a standby input, the switch transistor is coupled between the level shifter circuit and the true ground, wherein when the logic input is at logic “0” and the standby input is at logic “1” the switch transistor is off and prevents sneak leakage current through the level shifter circuit.
3 more elements
An integrated circuit device having conditional back bias virtual ground restoration circuits for preventing sneak leakage currents and shifting a virtual ground level logic “0” to a true ground level logic “0” when logic “0” signals at the virtual ground level are applied in the integrated circuit device, comprising:
- at least one independent voltage domain operating at a virtual ground and at least one other independent voltage domain operating at a true ground, wherein the virtual ground is at a more positive voltage than the true ground;
- a plurality of conditional back bias virtual ground restoration circuits, each of the plurality of conditional back bias virtual ground restoration circuits is coupled between one of a plurality of first logic circuits operating in the virtual ground voltage domain and one of a plurality of second logic circuit operating in the true ground voltage domain, wherein the plurality of first and second logic circuits operating in the virtual and true ground voltage domains, respectively, are fabricated on an integrated circuit die, and
- wherein each of the plurality of ground restoration circuits comprises:
- a first P-channel metal oxide semiconductor (PMOS) transistor (202) having a gate, source, drain and bulk;
- a second PMOS transistor (204) having a gate, source, drain and bulk;
- a first N-channel metal oxide semiconductor (NMOS) transistor (208) having a gate, source, drain and bulk;
- a second NMOS transistor (206) having a gate, source, drain and bulk;
- a third NMOS transistor (212) having a gate, source, drain and bulk;
- a fourth NMOS transistor (210) having a gate, source, drain and bulk;
- a first inverter (222) having an input and an output, wherein the first inverter (222) is coupled to the power source voltage and the virtual ground;
- a first NAND gate (216) having first and a second inputs and an output;
- a second NAND gate (218) having first and a second inputs and an output;
- the sources and bulk of the first PMOS transistor (202) and the second PMOS transistor (204) are coupled to the power source voltage;
- the drains of the first PMOS transistor (202) and the first NMOS transistor (208), the gate of the second PMOS transistor (204) and the first input of the first NAND gate (216) are coupled together;
- the drains of the second PMOS transistor (204) and second NMOS transistor (206), the gate of the first PMOS transistor (202) and the first input of the second NAND gate (214) are coupled together;
- the gate of the first NMOS transistor (208) and the input of the first inverter (222) are coupled to a logic signal from a logic circuit operating in the virtual ground voltage domain;
- the output of the first inverter (222) is coupled to the gate of the second NMOS transistor (206);
- the source of the first NMOS transistor (208) are coupled to the drain of the fourth NMOS transistor (212) and the bulk of the first NMOS transistor (208) is coupled to true ground;
- the source of the second NMOS transistor (206) are coupled to the drain of the third NMOS transistor (210) and the bulk of the second NMOS transistor (206) is coupled to true ground;
- the sources and bulks of the third NMOS transistor (210) and the fourth NMOS transistor (212) are coupled to the true ground;
- and
- the second inputs of the first and second NAND gates (216, 214) are coupled to a standby signal,
- wherein when the logic signal from the logic circuit is at logic “0” and the standby signal is at logic “1” the output of the first NAND gate (216) is at logic “0” whereby the fourth NMOS transistor (212) is off and thereby prevents sneak leakage current therethrough.
20 more elements
A conditional back bias virtual ground restoration circuit for preventing sneak leakage currents and shifting a virtual ground level logic “0” to a true ground level logic “0” when a logic “0” signal at a virtual ground level is present, comprising:
- a first P-channel metal oxide semiconductor (PMOS) transistor (202) having a gate, source, drain and bulk;
- a second PMOS transistor (204) having a gate, source, drain and bulk;
- a first N-channel metal oxide semiconductor (NMOS) transistor (208) having a gate, source, drain and bulk;
- a second NMOS transistor (206) having a gate, source, drain and bulk;
- a third NMOS transistor (212) having a gate, source, drain and bulk;
- a fourth NMOS transistor (210) having a gate, source, drain and bulk;
- a first inverter (222) having an input and an output, wherein the first inverter (222) is coupled to the power source voltage and the virtual ground;
- a first NAND gate (216) having first and a second inputs and an output;
- a second NAND gate (218) having first and a second inputs and an output;
- the sources and bulk of the first PMOS transistor (202) and the second PMOS transistor (204) are coupled to the power source voltage;
- the drains of the first PMOS transistor (202) and the first NMOS transistor (208), the gate of the second PMOS transistor (204) and the first input of the first NAND gate (216) are coupled together;
- the drains of the second PMOS transistor (204) and second NMOS transistor (206), the gate of the first PMOS transistor (202) and the first input of the second NAND gate (214) are coupled together;
- the gate of the first NMOS transistor (208) and the input of the first inverter (222) are coupled to a logic signal operating in the virtual ground voltage domain;
- the output of the first inverter (222) is coupled to the gate of the second NMOS transistor (206);
- the source of the first NMOS transistor (208) is coupled to the drain of the fourth NMOS transistor (212);
- the source of the second NMOS transistor (206) is coupled to the drain of the third NMOS transistor (210);
- the bulk of the first and second NMOS transistors (208, 206) are coupled to the true ground;
- the sources and bulks of the third NMOS transistor (210) and the fourth NMOS transistor (212) are coupled to the true ground;
- and
- the second inputs of the first and second NAND gates (216, 214) are coupled to a standby signal,
- wherein when the logic signal is at logic “0” and the standby signal is at logic “1” the output of the first NAND gate (216) is at logic “0” whereby the fourth NMOS transistor (212) is off and thereby prevents sneak leakage current therethrough.
18 more elements
Dependencies are inferred from the claim text.