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US 2010/0148375 A1Published application
Vertically Tapered Transmission Line for Optimal Signal Transition in High-Speed Multi-Layer Ball Grid Array Packages
AssigneeAltera Corporation
InventorsXiaohong Jiang, Hong Shi
Life of this patent
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Abstract
Broadly speaking, the embodiments of the present invention fill the need for methods of designing vertical transmission lines for optimal signal transition in multi-layer BGA packages. By controlling the impedance and geometry continuity of micro vias in each micro via layer in the package to follow smooth impedance and geometry curves from layer to layer, the return loss and insertion loss of the transmission line can be reduced or controlled to within acceptable ranges.
Claims20
A package substrate for a semiconductor chip, comprising:
- a core layer;
- a conductive layer disposed over a top and a bottom surface of the core layer;
- a dielectric layer disposed over an outer surface of each conductive layer, wherein additional conductive layers and dielectric layers are disposed over each other in an alternating fashion, and wherein each dielectric layer includes multiple signal vias extending therethrough;
- and
- a plated through hole extending between the top and bottom surface of the core layer, wherein a central area of each of the multiple signal vias of different dielectric layers of the package substrate is linearly aligned with a center of the plated through hole.
2 more elements
A package substrate, comprising:
- a core layer having a plated through hole extending between top and bottom surfaces of the core layer;
- and
- alternating conductive and dielectric layers disposed over each other and extending out from a surface of the core layer, wherein each dielectric layer includes a signal via extending therethrough, each signal via linearly aligned with the plated through hole and signal vias of each dielectric layer, and wherein each dielectric layer includes a ground via extending therethrough, wherein a central region of each ground via is linearly aligned with a center of the plated through hole.
A package for a semiconductor chip, comprising:
- a semiconductor chip;
- a printed circuit board;
- and
- a package substrate electrically connected to the semiconductor chip through a flip chip configuration, the package substrate electrically connected with the printed circuit board through a ball and grid array configuration, the package substrate having a core layer with a plated through hole extending between top and bottom surfaces of the core layer, top and bottom surfaces of the core layer having alternating conductive and dielectric layers disposed over each other, wherein each dielectric layer includes a signal via extending therethrough, each signal via linearly aligned with the plated through hole and signal vias of each dielectric layer.
1 more element
Dependencies are inferred from the claim text.