Stacked Die Parallel Plate Capacitor
AssigneeQUALCOMM Incorporated
InventorArvind Chandrasekaran
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Abstract
A stacked integrated circuit having a first die with a first surface and a second die with a second surface facing the first surface, the stacked integrated circuit includes a capacitor. The capacitor is formed by a first conducting plate on a region of the first surface, a second conducting plate on a region of the second surface substantially aligned with the first conducting plate, and a dielectric between the first conducting electrode and the second conducting electrode.
Claims20
A stacked integrated circuit having a first die with a first surface and a second die with a second surface facing the first surface, the stacked integrated circuit comprising:
- a capacitor formed by a first conducting plate on a region of the first surface, a second conducting plate on a region of the second surface substantially aligned with the first conducting plate, and a dielectric between the first conducting electrode and the second conducting electrode.
A stacked integrated circuit, comprising:
- a first die, having a first surface comprising a first conducting plate;
- a second die stacked with the first die, the second die having a second surface facing the first surface of the first die, the second surface comprising a second conducting plate opposing the first conducting plate;
- and
- an insulator between the first die and the second die,
- wherein the first conducting plate, the second conducting plate, and the insulator form a capacitor.
Dependencies are inferred from the claim text.