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US 2010/0148343 A1Published application
Side stacking apparatus and method
AssigneeCufer Asset Ltd. L.L.C.
InventorJohn Trezza
Life of this patent
Estimating the term…
Abstract
A module has at least two ICs connected to each other such that they lie in different planes and are arranged as a first stack of ICs, a third IC is connected to at least one of the at least two ICs, wherein the third IC is off plane from both of the at least two ICs.
Claims51
A module comprising:
- a first integrated circuit (IC) electrically connected to a second IC by a physical connection located between facing surfaces of the first and second ICs;
- and
- a third IC electrically connected to the physical connection, wherein the third IC is substantially perpendicular to the first and second ICs.
A module comprising:
- a stack of integrated circuits (ICs) including a first IC that is electrically connected to a second IC by a physical connection located between the first and second ICs;
- and
- a third IC positioned along a lateral surface of the stack, wherein the third IC is electrically connected to at least one of the first or second ICs at the physical connection located between the first and second ICs.
A module comprising:
- a first integrated circuit (IC) electrically coupled to both a second IC and a third IC at a common connection point, wherein the third IC is arranged substantially perpendicular to the first and second ICs.
A method comprising:
- connecting a first integrated circuit (IC) to a second IC to form a stack of ICs;
- and
- connecting a third IC to at least one of the first or second ICs at a connection point located between facing surfaces of the first and second ICs, wherein the third IC is substantially perpendicular to the first and second ICs.
A method comprising:
- connecting a first integrated circuit (IC) to a second integrated circuit to form a stack of ICs;
- positioning a third IC on a lateral surface of the stack of ICs;
- and
- connecting the third IC to at least one of the first or second ICs at a connection point located between facing surfaces of the first and second ICs.
1 more element
Dependencies are inferred from the claim text.