Stackable semiconductor package and process to manufacture same

A multiple electrical device package comprising:

• a) a semiconductor device in a wafer having a plurality of contacts on an upper surface of said wafer;
• b) a first plurality of traces attached to the top of said wafer;
• c) a second plurality of vertical posts attached to said first plurality of traces;
• d) an electrical device bonded to at least some of said first plurality of traces;
• and
• e) encapsulation material enclosing said electrical device and sides of said first plurality of traces and sides of said second plurality of vertical posts such that tops of said vertical posts are exposed on the top of said semiconductor package.

A method for forming a stackable electrical device package comprising the steps of:

• a) forming a first plurality of traces on a sacrificial wafer;
• b) forming a second plurality of vertical posts on said first plurality of traces;
• c) attaching said electrical device to at least some of said first plurality of traces;
• and
• d) encapsulating said electrical device and sides of said first plurality of traces and sides of said second plurality of vertical posts;
• e) removing said sacrificial wafer such that bottoms of said first plurality of traces are exposed on the bottom of said semiconductor package, and tops of said vertical posts are exposed on the top of said semiconductor package.

A method for forming a multiple electrical device package comprising the steps of:

• a) forming a first plurality of traces on a semiconductor wafer having a second plurality of contacts on an upper surface of said wafer, wherein at least some of said first plurality of traces are attached to at least some of said second plurality of contacts;
• b) forming a third plurality of vertical posts on said first plurality of traces;
• c) attaching an electrical device to at least some of said first plurality of traces;
• and
• d) encapsulating said electrical device and sides of said first plurality of traces and sides of said second plurality of vertical posts such that tops of said vertical posts are exposed on the top of said semiconductor package.