Integrated circuit packaging system having through silicon vias with partial depth metal fill regions and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system comprising:

• providing a silicon substrate having circuitry in a circuitry layer;
• creating a partial via through the circuitry in the circuitry layer;
• filling the partial via with a plug having a bottom surface;
• creating a recess that is angled outward and exposes the bottom surface of the plug;
• coating the recess with a recess-insulation-layer while leaving the bottom surface of the plug exposed to create a through-silicon-via-die;
• connecting the silicon substrate to a substrate;
• and
• encapsulating the silicon substrate with an encapsulation.

An integrated circuit packaging system comprising:

• a silicon substrate having circuitry in a circuitry layer;
• a partial via created through the circuitry in the circuitry layer;
• a plug having a bottom surface that fills the partial via;
• a recess that is angled outward and exposes the bottom surface of the plug;
• and
• a recess-insulation-layer that coats the recess while leaving the bottom surface of the plug exposed.