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US 2010/0148326 A1Published application
Thermally Enhanced Electronic Package
AssigneeInfineon Technologies North America Corp.
InventorsAnwar A. Mohammad, Julius Chew
Life of this patent
Estimating the term…
Abstract
According to one embodiment, an electronic package includes a semiconductor die, a heat sink and a metallization layer interposed between the semiconductor die and the heat sink. The metallization layer attaches the semiconductor die to the heat sink. The metallization layer has a thickness of about 5 μm or less and a thermal conductivity of about 60 W/m·K or greater.
Claims24
An electronic package, comprising:
- a semiconductor die;
- a heat sink;
- and
- a metallization layer interposed between the semiconductor die and the heat sink which attaches the semiconductor die to the heat sink, the metallization layer having a thickness of about 5 μm or less and a thermal conductivity of about 60 W/m·K or greater.
1 more element
A method of manufacturing an electronic package, comprising:
- placing a semiconductor die on a lead frame so that a metallization layer arranged on a surface of the semiconductor die is interposed between the semiconductor die and the lead frame, the metallization layer having a thickness of about 5 μm or less and a thermal conductivity of about 60 W/m·K or greater;
- and
- applying an elevated temperature and a force of at least 70N to the semiconductor die and the lead frame so that the metallization layer attaches the semiconductor die to the lead frame.
An electronic package, comprising:
- a semiconductor die;
- a lead frame;
- a metallization layer interposed between the semiconductor die and the lead frame which attaches the semiconductor die to the lead frame, the metallization layer having a thickness of about 5 μm or less and a thermal conductivity of about 60 W/m·K or greater;
- and
- a plastic molding compound formed over the semiconductor die and the lead frame.
2 more elements
A method of manufacturing an electronic package, comprising:
- depositing on a semiconductor wafer a metallization layer having a thickness of about 5 μm or less and a thermal conductivity of about 60 W/m·K or greater;
- dicing the semiconductor wafer into a plurality of dies;
- placing at least one of the dies on a lead frame so that the metallization layer is interposed between the at least one die and the lead frame;
- and
- applying an elevated temperature and a force of at least 70N to the at least one die and the lead frame so that the metallization layer attaches the at least one die to the lead frame.
2 more elements
Dependencies are inferred from the claim text.