Bipolar integration without additional masking steps
AssigneeX-Fab Semiconductor Foundries AG
InventorsThomas Uhlig, Felix Fuernhammer, Christoph Ellmers
Life of this patent
Estimating the term…
Loading patent…
AssigneeX-Fab Semiconductor Foundries AG
InventorsThomas Uhlig, Felix Fuernhammer, Christoph Ellmers
Estimating the term…
The invention relates to a BiMOS semiconductor component having a semiconductor substrate wherein, in a first active region, a depletion-type MOS transistor is formed comprising additional source and drain doping regions of the first conductivity type extending in the downward direction past the depletion region into the body doping region while, in a second active region, (101), a bipolar transistor (100) is formed, the base of which comprises a body doping region (112) and the collector of which comprises a deep pan (110), wherein an emitter doping region (114) of the first conductivity type and a base connection doping region (118) of the second conductivity type are formed in the body doping region. The semiconductor element can be produced with a particularly low process expenditure because it uses the same basic structure for the doping regions in the bipolar transistor as are used in the MOS transistor of the same semiconductor component.
A BiMOS semiconductor device including a semiconductor substrate which comprises in first and second active regions delineated by a field isolation region the following doped regions
The BiMOS semiconductor device of any of the preceding claims, wherein said doped emitter region has an extension in the depth direction between 100 and 300 nanometer.
The BiMOS semiconductor device of any of the preceding claims, wherein said doped body region has an extension in the depth direction between 300 and 700 nanometer.
The BiMOS semiconductor device of any of the preceding claims, wherein a distance between a lower boundary of the doped emitter region facing away from the substrate surface and an upper boundary of the deep well facing the substrate surface is between 100 and 300 nanometer.
The BiMOS semiconductor device, wherein in the second active region in a lateral region between said doped emitter region and said doped base junction region an implant of the first conductivity type is superimposed on said third doped region so as to avoid recharging effects at the substrate surface.
The BiMOS semiconductor device of any of the preceding claims, comprising a third active region in which a SONOS storage element is formed, wherein a channel region of the SONOS storage element comprises said second doped region.
The BiMOS semiconductor device of any of the preceding claims, further comprising, in addition to said MOS transistor, a complementary MOS transistor of the depletion type, of which, contrary to said MOS transistor, the doped source, drain and body regions and the deep well are of the inverse conductivity type.
A method of forming a BiMOS semiconductor device, the method comprising the steps
Dependencies are inferred from the claim text.