US 2010/0148273 A1 · CMOS TRANSISTORS WITH DIFFERENTIAL OXYGEN CONTENT HIGH-K DIELECTRICS

Abstract

An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.

Claims12

Dependent claims

A semiconductor structure comprising:

a first field effect transistor including:
a first high-k dielectric portion vertically abutting a semiconductor substrate;
a first metal gate vertically abutting said first high-k dielectric portion;
a first silicon containing gate conductor vertically abutting said first metal gate;
and
an oxide spacer laterally abutting said first metal gate and said first silicon containing gate conductor;
and
a second field effect transistor including:
a second high-k dielectric portion vertically abutting said semiconductor substrate;
a second metal gate vertically abutting said second high-k dielectric portion;
a second silicon containing gate conductor vertically abutting said second metal gate;
and
a gate sidewall nitride laterally abutting said second metal gate and said second silicon containing gate conductor, wherein said second high-k dielectric portion is more stoichiometric than said first high-k dielectric portion.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application

12/712,371Filed 25 Feb 2010

Priority

14 Jun 2007

Published

17 Jun 2010

Term ends

Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/792
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: comprising applied insulating layers, e.g. stress liners
H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain

Cmos transistors with differential oxygen content high-k dielectrics

Life of this patent

Cmos transistors with differential oxygen content high-k dielectrics

Life of this patent

Abstract

Claims12