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US 2010/0148270 A1Published application
Methods of channel stress engineering and structures formed thereby
AssigneeIntel Corporation
InventorsOleg Golonzka, Hemant Deshpande, Ajay K. Sharma, Cory Weber, Ashutosh Ashutosh
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Abstract
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a source/drain region in an NMOS portion of a substrate, wherein the source/drain region of the NMOS portion comprises at least one dislocation, and wherein a PMOS source/drain region in a PMOS portion of the substrate does not comprise a dislocation.
Claims30
A method comprising:
- amorphizing a source/drain region of an NMOS portion of a substrate comprising an NMOS gate, wherein a PMOS portion of the substrate is not amorphized;
- forming a stress material on a top surface and on a sidewall region of the NMOS gate and the PMOS gate;
- and
- annealing the stress material, wherein a dislocation is formed adjacent a channel region of the NMOS portion of the substrate.
1 more element
A method comprising:
- exposing an NMOS portion of a substrate and masking a PMOS portion of the substrate with a masking material;
- amorphizing a source/drain region of the NMOS portion of the substrate by ion implantation;
- removing the masking material from the PMOS portion of the transistor substrate;
- forming a tensile material on an NMOS gate of the NMOS portion of the substrate and on a PMOS gate of the PMOS portion of the substrate;
- and
- annealing the tensile material, wherein a dislocation is formed adjacent a channel region of the NMOS portion of the substrate that introduces a strain into an NMOS channel region adjacent the dislocation.
3 more elements
A structure comprising:
- a source/drain region disposed in an NMOS portion of a substrate, wherein the source/drain region comprises at least one dislocation, and wherein a PMOS source/drain region of a PMOS portion of the substrate does not comprise a dislocation.
A structure comprising:
- a transistor substrate comprising an NMOS portion and a PMOS portion;
- an NMOS gate disposed on the NMOS portion and a PMOS gate disposed on the PMOS portion, wherein a source/drain region disposed in the NMOS portion comprises at least one dislocation, and wherein a source/drain region disposed in the PMOS portion of the substrate does not comprise a dislocation;
- and
- a strained channel region disposed in the NMOS portion, wherein the strained channel region is adjacent to the at least one dislocation.
1 more element
Dependencies are inferred from the claim text.