Lateral diffused metal oxide semiconductor (ldmos) devices with electrostatic discharge (esd) protection capability in integrated circuit

A lateral diffused P-type metal oxide semiconductor (LDPMOS) device with electrostatic discharge (ESD) protection capability, comprising:

• a semiconductor substrate with an epi-layer thereon;
• patterned isolations disposed on the epi-layer, thereby defining an active region;
• a P-type double diffused drain (PDDD) region formed in the active region;
• a P+ heavily doped drain region disposed in the PDDD region;
• a neighboring pair of an N+ heavily doped and a P+ heavily doped source region disposed in the epi-layer;
• and
• a gate structure is disposed between the P+ heavily doped source region and the P+ heavily doped drain region,
• wherein an additional heavily doped region is formed between the semiconductor substrate and the epi-layer.

A lateral diffused N-type metal oxide semiconductor (LDNMOS) device with electrostatic discharge (ESD) protection capability, comprising:

• 3 a semiconductor substrate with an epi-layer thereon;
• patterned isolations disposed on the epi-layer, thereby defining an active region;
• an N-type double diffused drain (NDDD) region formed in the active region;
• an N+ heavily doped drain region disposed in the NDDD region;
• a neighboring pair of an N+ heavily doped and a P+ heavily doped source region disposed in the epi-layer;
• and
• a gate structure is disposed between the N+ heavily doped source region and the N+ heavily doped drain region,
• wherein an additional heavily doped region is formed between the semiconductor substrate and the epi-layer.

A lateral diffused P-type metal oxide semiconductor (LDPMOS) device with electrostatic discharge (ESD) protection capability, comprising:

• a semiconductor substrate with an epi-layer thereon;
• a buried layer disposed between the semiconductor substrate and the epi-layer;
• patterned isolations disposed on the epi-layer, thereby defining a first active region and a second active region;
• a P-type double diffused drain (PDDD) region formed in the first active region;
• a P+ heavily doped drain region disposed in the PDDD region;
• an N-body diffused region formed in the second active region, wherein the PDDD region and the N-body diffused region are separated with a predetermined distance exposing the semiconductor substrate;
• a neighboring pair of an N+ heavily doped and a P+ heavily doped source region disposed in the N-body diffused region;
• and
• a gate structure is disposed between the P+ heavily doped source region and the P+ heavily doped drain region,
• wherein an additional heavily doped region is formed between the semiconductor substrate and the epi-layer.