Semiconductor device having transistor and method of manufacturing the same

A method of manufacturing a semiconductor device, the method comprising:

• forming an isolation region within a substrate to define an active region including an edge portion that is adjacent to an interface of the isolation region and the active region and a center portion that is surrounded by the edge portion;
• forming a gate insulating layer on the active region;
• forming a gate pattern on the gate insulating layer, the gate pattern overlapping the center portion and the edge portion of the active region and the isolation region;
• and
• simultaneously forming a source region, a drain region, and a first impurity region, wherein all of the source region, the drain region, and the first impurity region are doped with impurities of a first conductivity type, wherein the source region and the drain region are formed in the center portion of the active region, and wherein the first impurity region is formed selectively within a center gate portion of the gate pattern overlapping the center portion of the active region with respect to an edge gate portion of the gate pattern overlapping the edge portion of the active region.

A method of manufacturing a semiconductor device, the method comprising:

• forming an isolation region within a substrate to define an active region including an edge portion that is adjacent to an interface of the isolation region and the active region and a center portion that is surrounded by the edge portion;
• forming a gate insulating layer on the active region;
• forming a gate pattern on the gate insulating layer, the gate pattern including a center gate portion overlapping the center portion of the active region and a ring-shaped edge gate portion partially overlapping the edge portion of the active region, wherein the ring-shaped edge gate portion extends along a first side wall, a second sidewall, a third sidewall and a fourth sidewall of the gate electrode, the first sidewall and the seconds sidewall being located on both sides of the center gate portion in a first direction and overlapping the isolation region, and the third sidewall and the fourth sidewall being located on both sides of the center gate portion in a second direction that is perpendicular to the first direction and overlapping the active region;
• and
• forming a first impurity region of a first conductivity type selectively within the center gate portion of the gate pattern with respect to the ring-shaped edge gate portion of the gate pattern.