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US 2010/0148234 A1Published application
Subresolution silicon features and methods for forming the same
AssigneeMicron Technology, Inc.
InventorsKevin J. Torek, Mark Fischer, Robert J. Hanson
Life of this patent
Estimating the term…
Abstract
Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch.
Claims20
An integrated circuit, comprising:
- an active area mesa surrounded by field isolation material, the mesa including a source region, a drain region and a channel region between the source and drain regions;
- a semiconductor fin protruding from the channel region of the mesa, the source and drain regions being substantially planar;
- and
- a gate electrode conforming to the surfaces of the fin in the channel region.
1 more element
A Fin FET device comprising:
- a mesa of semiconductor material on a semiconductor substrate, wherein the mesa comprises a contoured portion, wherein the mesa is surrounded on lateral sides by an isolation material, and wherein the isolation material is recessed relative to the contoured portion;
- a gate dielectric conformally covering the contoured portion of the mesa;
- and
- a gate conductor conformally covering the gate dielectric covering the contoured portion of the mesa.
1 more element
A semiconductor structure comprising:
- a semiconductor mesa surrounded by field isolation regions, wherein the semiconductor mesa comprises a rounded portion;
- and
- a gate dielectric conformally covering the rounded portion of the semiconductor mesa.
Dependencies are inferred from the claim text.