Jfet device structures and methods for fabricating the same
AssigneeMicron Technology, Inc.
InventorChandra Mouli
Life of this patent
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Abstract
In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.
Claims44
A transistor comprising:
- a semiconductor substrate comprising a source and a drain;
- a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain;
- a gate comprising a semiconductor material formed over the channel;
- and
- dielectric spacers located on each side of the gate,
- wherein the source and the drain are spatially separated from the gate so that the gate is not located over the source and drain.
A transistor comprising:
- a substrate material;
- silicon formed over the substrate;
- a channel formed in the silicon;
- a gate formed over the channel;
- and
- a source and drain formed in the silicon on opposing sides of the channel, wherein the source and drain do not extend under the gate.
A semiconductor device comprising:
- a first level of one or more transistors, the first level comprising:
- a first insulative substrate;
- a first semiconductor formed over the substrate;
- a first gate formed over the semiconductor;
- and
- first insulative spacers formed on each side of the gate;
- and
- a second level comprising one or more transistors, the second level comprising:
- a second insulative substrate formed over the first level;
- a second semiconductor formed over the second substrate;
- a second gate formed over the second semiconductor;
- and
- second insulative spacers formed on each side of the second gate.
A multi-level device comprising:
- a first level comprising a first plurality of transistors;
- and
- a second level formed over the first level, the second level comprising a second plurality of transistors, wherein each of the first and second plurality of transistors comprises:
- a doped insulative material;
- a semiconductor formed over the doped insulative material;
- and
- a gate formed over the semiconductor, wherein the gates of the transistors of the second level are shorter than the gates of the transistors of the first level.
A method of fabricating a transistor comprising:
- doping an insulator;
- forming a semiconductor substrate over the doped insulator;
- doping regions of the semiconductor substrate to create a source region, a drain region and a channel region;
- forming a gate over the channel region;
- and
- forming spacers adjacent to the gate, wherein the source and drain regions of the semiconductor are separated from the gate a distance commensurate with the width of the spacers.
A method of fabricating multi-level transistors wherein each level comprises:
- doping an insulator;
- forming a semiconductor substrate over the doped insulator;
- doping regions of the semiconductor substrate to create a source region, a drain region and a channel region;
- forming a gate over the channel region;
- and
- forming spacers adjacent to the gate, wherein the source and drain regions of the semiconductor are separated from the gate a distance commensurate with the width of the spacers.
Dependencies are inferred from the claim text.