Semiconductor device and method of manufacturing the same
AssigneeKabushiki Kaisha Toshiba
InventorZhengwu Jin
Life of this patent
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Abstract
A semiconductor device includes an insulated-gate field-effect transistor which is disposed on a semiconductor substrate having an element formation plane in a (110) plane direction, and which has a channel length direction in a <−110> direction, and a first element isolation insulation film which is buried in a trench in an element isolation region of the semiconductor substrate and has a positive expansion coefficient, the first element isolation insulation film applying a compressive stress by operation heat to the insulated-gate field-effect transistor in the channel length direction.
Claims20
A semiconductor device comprising:
- an insulated-gate field-effect transistor which is disposed on a semiconductor substrate having an element formation plane in a (110) plane direction, and which has a channel length direction in a <−110> direction;
- and
- a first element isolation insulation film which is buried in a trench in an element isolation region of the semiconductor substrate and has a positive expansion coefficient, the first element isolation insulation film applying a compressive stress by operation heat to the insulated-gate field-effect transistor in the channel length direction.
A semiconductor device comprising:
- a p-type insulated-gate field-effect transistor which is disposed on a semiconductor substrate having an element formation plane in a (110) plane direction, and which has a channel length direction in a <−110> direction;
- a first element isolation insulation film which is buried in a trench in an element isolation region of the semiconductor substrate and has a positive expansion coefficient, the first element isolation insulation film applying a compressive stress by operation heat to the p-type insulated-gate field-effect transistor in the channel length direction;
- an n-type insulated-gate field-effect transistor which is disposed on a semiconductor substrate having an element formation plane in a (100) plane direction, and which has a channel length direction in a <100> direction;
- and
- a second element isolation insulation film which is buried in a trench in an element isolation region of the semiconductor substrate and has a negative expansion coefficient, the second element isolation insulation film applying a tensile stress by operation heat to the n-type insulated-gate field-effect transistor in the channel length direction.
A method of manufacturing a semiconductor device, comprising:
- forming a trench for element isolation in an element isolation region of a semiconductor substrate along two axial directions that are a channel width direction and a channel length direction, the semiconductor substrate having an element formation plane in a (100) plane direction;
- burying a silicon oxide film in the trench, thereby forming a first element isolation insulation film;
- doping a crystal seed only in the silicon oxide film extending in the channel length direction;
- performing a first heat treatment process on the silicon oxide film doped the crystal seed, thereby making the silicon oxide film transition into a glass state;
- performing a second heat treatment process on the silicon oxide film that is in the glass state, thereby precipitating a crystal nucleus in an amorphous matrix layer in the silicon oxide film;
- performing a third heat treatment process on the amorphous matrix layer including the crystal nucleus, thereby growing the crystal nucleus into a crystal line and forming a second element isolation insulation film including a glass ceramics layer;
- forming a gate insulation film on the semiconductor substrate in an element region;
- forming a gate electrode on the gate insulation film such that the channel length direction is set in a <−110> direction;
- and
- forming a source and a drain spaced apart in the semiconductor substrate in a manner to sandwich the gate electrode.
Dependencies are inferred from the claim text.