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US 2010/0148218 A1Published application
Semiconductor integrated circuit device and method for designing the same
AssigneePanasonic Corporation
InventorKenji YOKOYAMA
Life of this patent
Estimating the term…
Abstract
The layout of an LSI is previously designed so that cells below pads which will be affected by stress are arranged so that the occurrence of a malfunction of the LSI which will be caused by the influence of stress is reduced or prevented. In addition to or instead of the cell arrangement, the arrangement of pads, bumps or the like may be adjusted.
Claims29
A semiconductor integrated circuit device comprising:
- a semiconductor chip including a plurality of input/output cells;
- a plurality of pads formed on a surface of the semiconductor chip;
- a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads;
- a first type cell formed in the semiconductor chip and configured not to cause the semiconductor chip to perform erroneous operation even if variations in timing occur;
- and
- a second type cell formed in the semiconductor chip and configured to cause the semiconductor chip to perform erroneous operation if variations in timing occur,
- wherein
- the density of the first type cells is higher than the density of the second type cells in an internal region of the semiconductor chip located below each of the plurality of pads.
5 more elements
A semiconductor integrated circuit device comprising:
- a semiconductor chip including a plurality of input/output cells;
- a plurality of pads formed on a surface of the semiconductor chip;
- a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads;
- and
- a first type cell formed in the semiconductor chip and configured not to cause the semiconductor chip to perform erroneous operation even if variations in timing occur,
- wherein
- the density of the first type cells is higher than or equal to a predetermined value in an internal region of the semiconductor chip located below one of the plurality of pads that is electrically connected to one of the plurality of input/output cells.
4 more elements
A semiconductor integrated circuit device comprising:
- a semiconductor chip including a plurality of input/output cells;
- a plurality of pads formed on a surface of the semiconductor chip;
- a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads;
- and
- a first type cell formed in the semiconductor chip and configured not to cause the semiconductor chip to perform erroneous operation even if variations in timing occur,
- wherein
- at least two of the plurality of pads are electrically connected to the same input/output cell, and
- a bump is selectively provided on one of the at least two pads that has a relatively high density of the first type cells provided in an internal region of the semiconductor chip located therebelow.
5 more elements
A semiconductor integrated circuit device comprising:
- a semiconductor chip including a plurality of input/output cells;
- a plurality of pads formed on a surface of the semiconductor chip;
- a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads;
- and
- a first type cell formed in the semiconductor chip and configured not to cause the semiconductor chip to perform erroneous operation even if variations in timing occur,
- wherein
- at least two of the plurality of pads are electrically connected to the same input/output cell, and
- on one of the at least two pads that has a relatively low density of the first type cells provided in an internal region of the semiconductor chip located therebelow, a bump having a smaller diameter than those of bumps on the other pads is formed.
5 more elements
A semiconductor integrated circuit device comprising:
- a semiconductor chip including a plurality of input/output cells;
- a plurality of pads formed on a surface of the semiconductor chip;
- and
- a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads,
- wherein
- all of the plurality of pads are electrically connected to the wire.
3 more elements
A semiconductor integrated circuit device comprising:
- a semiconductor chip including a plurality of input/output cells;
- a plurality of pads formed on a surface of the semiconductor chip;
- and
- a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads,
- wherein
- a bump is selectively provided on one of the plurality of pads that is electrically connected to the wire.
3 more elements
A semiconductor integrated circuit device comprising:
- a semiconductor chip including a plurality of input/output cells;
- a plurality of pads formed on a surface of the semiconductor chip;
- and
- a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads,
- wherein
- on one of the plurality of pads that is not electrically connected to the wire, a bump having a smaller diameter than those of bumps on the other pads is formed.
3 more elements
A semiconductor integrated circuit device comprising:
- a semiconductor chip including a plurality of input/output cells;
- a plurality of pads formed on a surface of the semiconductor chip;
- and
- a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads,
- wherein
- of the plurality of input/output cells, the plurality of pads and the wire, an input/output cell, a pad and a wire which are provided in one hierarchical block are arranged so that the one hierarchical block can be operated singly.
3 more elements
A semiconductor integrated circuit device comprising:
- a semiconductor chip including a plurality of input/output cells;
- a plurality of pads formed on a surface of the semiconductor chip;
- and
- a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads,
- wherein
- the surface of the semiconductor chip is covered with a passivation layer having an opening portion on each of the plurality of pads, and
- the opening portion is in the shape of a polygon having four or more corners or a circle.
4 more elements
Dependencies are inferred from the claim text.