Package structure for chip and method for forming the same

A method for forming a package structure for chip, comprising:

• providing a carrier substrate having an upper surface and an opposite lower surface;
• forming a stacked hole serving as a first through-hole penetrating the upper surface and the lower surface of the carrier substrate;
• forming a first conducting layer overlying a sidewall of the first through-hole;
• forming a third conducting structure overlying the carrier substrate and comprising a second through-hole;
• disposing a light emitting chip over the carrier substrate, wherein the light emitting chip has a first surface and an opposite second surface facing the upper surface and comprises a first electrode and a second electrode;
• forming a first conducting structure overlying the carrier substrate and electrically connecting the first electrode and the first conducting layer;
• and
• forming a second conducting structure overlying the carrier substrate and electrically connecting the second electrode and the third conducting structure.

A method for forming a package structure for chip, comprising:

• providing a semiconductor wafer having an upper surface and an opposite lower surface;
• forming a stacked hole serving as a first through-hole penetrating the upper surface and the lower surface of the semiconductor wafer;
• forming a first conducting layer overlying a sidewall of the first through-hole;
• forming a third conducting structure overlying the semiconductor wafer and comprising a second through-hole;
• dicing the semiconductor wafer to form a plurality of carrier substrates for packaging;
• disposing a light emitting chip over one of the carrier substrates, wherein the light emitting chip has a first surface and an opposite second surface facing the upper surface and comprises a first electrode and a second electrode;
• forming a first conducting structure overlying the carrier substrate and electrically connecting the first electrode and the first conducting layer;
• and
• forming a second conducting structure overlying the carrier substrate and electrically connecting the second electrode and the third conducting structure.