Vertical junction field effect transistors having sloped sidewalls and methods of making
AssigneeSemisouth Laboratories, Inc.
InventorsDavid C. Sheridan, Andrew P. Ritenour
Life of this patent
Estimating the term…
Abstract
Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.
Claims32
A semiconductor device comprising:
- a substrate layer of a semiconductor material of a first conductivity type;
- a channel layer of a semiconductor material of the first conductivity type on an upper surface of the substrate layer, the channel layer comprising one or more raised regions comprising an upper surface and first and second sidewalls separated by a lower surface, wherein the first and second sidewalls of the raised regions adjacent the lower surface are tapered inward and form an angle of at least 5° from vertical to the upper surface of the substrate layer, wherein the one or more raised regions comprises an inner portion of a semiconductor material of the first conductivity type and outer portions of a semiconductor material of a second conductivity type different than the first conductivity type, wherein the outer portions are adjacent to the first and second sidewalls;
- gate regions of semiconductor material of the second conductivity type in the lower surface of the channel layer adjacent to and contiguous with the outer portions of adjacent raised regions;
- and
- a source layer of a semiconductor material of the first conductivity type on the upper surfaces of the one or more raised regions.
A method comprising:
- implanting ions into a channel layer of a semiconductor material of a first conductivity type to form implanted gate regions of semiconductor material of a second conductivity type different than the first conductivity type, wherein the channel layer is on an upper surface of a substrate layer and wherein the channel layer comprises one or more raised regions comprising an upper surface and first and second sidewalls separated by a lower surface, wherein the first and second sidewalls of the raised regions adjacent the lower surface are tapered inward and form an angle of at least 5° from vertical to the upper surface of the substrate, wherein the implanted gate regions are formed in the sidewalls and in the lower surface of the channel layer;
- and
- forming a source layer of a semiconductor material of the first conductivity type on the upper surfaces of the one or more raised regions.
Dependencies are inferred from the claim text.