US 2010/0148182 A1 · THIN FLIM TRANSISTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF

Abstract

A thin film transistor (TFT) substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion and a method of fabricating the TFT substrate. The TFT substrate includes a gate interconnection line formed on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode and a drain electrode formed on the semiconductor layer, a first passivation layer formed on the data interconnection line and exposing the drain electrode, a second passivation layer formed on the first passivation film and a pixel electrode electrically connected to the drain electrode. An outer sidewall of the second passivation layer is positioned inside an outer sidewall of the first passivation layer.

Claims12

Dependent claims

A thin film transistor (TFT) substrate, comprising:

a gate interconnection line comprising a gate line and a gate electrode arranged on an insulating substrate;
a gate insulating layer formed on the gate interconnection line;
a semiconductor layer formed on the gate insulating layer;
a data interconnection line comprising a data line, a source electrode, and a drain electrode formed on the semiconductor layer;
a first passivation layer formed on the data interconnection line and exposing a portion of the drain electrode;
a second passivation layer formed on the first passivation film, wherein the outer sidewalls of the second passivation film are positioned inside the outer sidewalls of the first passivation film;
and
a pixel electrode connected to the drain electrode.

5 more elements

A method of fabricating a thin film transistor (TFT) substrate comprising:

forming a gate interconnection line on an insulating substrate, the gate interconnection line comprising a gate line and a gate electrode;
forming a gate insulating layer on the gate interconnection line;
forming a semiconductor layer and a data interconnection line on the semiconductor layer, the data interconnection line comprising a data line, a source electrode, and a drain electrode;
sequentially forming a first passivation layer and a second passivation layer on the data interconnection line, the second passivation layer has more porous lattice structure than that of the first passivation layer;
etching the second passivation layer and the first passivation layer, and exposing a drain electrode of a drain electrode-pixel electrode contact portion;
and
forming a pixel electrode connected to the drain electrode,
wherein etching the second passivation layer and the first passivation layer comprises forming the outer sidewalls of the second passivation layer inside the outer sidewalls of the first passivation layer.

5 more elements

Dependencies are inferred from the claim text.

Thin flim transistor substrate and manufacturing method thereof

Life of this patent

Thin flim transistor substrate and manufacturing method thereof

Life of this patent

Abstract

Claims12