Thin film transistor, method of forming the same and flat panel display device having the same

A method of forming a thin film transistor (TFT), comprising:

• sequentially forming a buffer layer, a preliminary channel area, an insulating layer, and a gate electrode layer on a substrate;
• sequentially patterning the gate electrode layer and the insulating layer to expose a portion of the preliminary channel area, and forming a gate pattern;
• doping the exposed portion of the preliminary channel area with impurities using the gate pattern as a mask to define a channel area and form source and drain regions;
• forming a passivation layer over the entire surface of the substrate having the source and drain regions;
• etching portions of the passivation layer formed on the source and drain regions and the gate pattern to form a first contact hole, a second contact hole and a third contact hole which expose portions of the buffer layer;
• and
• forming a metal electrode layer over the entire surface of the substrate to fill the first contact hole, the second contact hole and the third contact hole.

A thin film transistor (TFT), comprising:

• a buffer layer and a semiconductor layer which are sequentially disposed on a substrate;
• a gate pattern including an insulating pattern and a gate electrode pattern which are sequentially disposed on the semiconductor layer;
• source and drain regions defining a portion of the semiconductor layer below the gate pattern as a channel area, formed by doping the semiconductor layer disposed at both sides of the gate pattern with impurities, and extending from both sides of the channel area;
• a passivation layer which covers the entire surface of the substrate having the gate pattern;
• a first metal electrode which penetrates a portion of the passivation layer disposed on the source area and a portion of the source region below the portion of the passivation layer to be electrically connected with the source region;
• and
• a second metal electrode which penetrates a portion of the passivation layer disposed on the drain area and a portion of the drain region below the portion of the passivation layer to be electrically connected with the drain region.

A flat panel display device, comprising:

• a buffer layer and a semiconductor layer which are sequentially disposed on a substrate;
• a gate pattern including an insulating pattern and a gate electrode pattern which are sequentially disposed on the semiconductor layer;
• source and drain regions defining a portion of the semiconductor layer below the gate pattern as a channel area, formed by doping the semiconductor layer disposed at both sides of the gate pattern with impurities, and extending from both sides of the channel area;
• a passivation layer which covers the entire surface of the substrate having the gate pattern;
• a first metal electrode which penetrates a portion of the passivation layer disposed on the source area and a portion of the source region below the portion of the passivation layer to be electrically connected with the source region;
• a second metal electrode which penetrates a portion of the passivation layer disposed on the drain area and a portion of the drain region below the portion of the passivation layer to be electrically connected with the drain region;
• a passivation insulating layer which covers the substrate having the second metal electrode;
• and
• an organic light-emitting diode disposed on the substrate having the passivation insulating layer to be electrically connected with the drain region.